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Tuesday, September 15, 2009

Power gating and dynamic frequency scaling

Moorestown's massive reduction in idle power draw is accomplished using the same basic technology, power gating, that Intel used to reduce Nehalem's idle power. Power gating lets Intel address the problem of leakage current, which I've gone into some detail on in a previous post. And, also like Nehalem, Intel has divide up the Lincroft SoC into different power and clock regions that can be downclocked or turned off independently of one another.

Also included is an increased number of clockspeed levels at which parts of the Lincroft SoC can operate. The idea here, as in all dynamic power optimization schemes, is to dynamically scale frequencies to match the workload. By adding more granular frequency scaling options for Lincroft's different functional blocks, the part can more closely fit its performance profile to a workload's needs within a given timeslice.

The main problem with doing this kind of dynamic frequency scaling aggressively in normal server or desktop computing applications is that there's always some latency involved in these power state transitions, and that latency saps performance. (In other words, all of the frequency scaling potential in the world is no good if the chip takes too long to react to and adapt to real-time changes in a workload.) But my guess is that this latency/performance issue is less critical in mobile applications for a variety of reasons (limited multitasking, relatively simple applications, low OS overhead, etc.), so Intel can just go nuts with the number of power states.

Intel has also extended this dynamic frequency scaling to Moorestown's memory bus, so that the platform can scale memory latency and bandwidth (and bus power draw) to match the current workload.

Moorestown also implements hyperthreading to boost performance-per-watt, but I really can't see this doing anything for a smartphone. This is a feature that will help Moorestown in netbooks, if the platform finds a use in that vertical.

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